I. Field of the Invention
This invention relates generally to a system and related method for sequentially providing data for an external circuit, and more specifically to a system and related method for sequentially providing an external circuit with operation instructions for use in controlling the operation of the external circuit.
II. Background Information
Systems for sequentially providing external circuit data for an external circuit which are known include a single-register system, referred to as a single pipeline sequencer, and a double-register system, referred to as a double pipeline sequencer. Conventional single and double pipeline sequencers may be used, for example, to sequentially provide an external circuit comprising an operating system with operating instructions.
As shown in the FIG. 1 depiction of the prior art, the typical single pipeline sequencer 100 includes control store memory 0, pipeline register 22, sequencer unit 24, and status select unit 26. The single pipeline sequencer 100 also includes data links 30, 32, 34, 36, 38, 40 and 42. Control store memory 20 is connected to pipeline register 22 by data link 30. Pipeline register 22 is coupled to sequencer unit 24 by data links 32 and 34; to status select unit 26 by data link 36; and to an external operating circuit 50 by data link 38. Status select unit 26 is coupled to sequencer unit 24 by data link 40. Sequencer unit 24 is coupled to control store memory 20 by data link 42.
Control store memory 20 stores sets of instructions, i.e., programs, at locations, each location having an address. Each location in control store memory 20 contains a program line or instruction which includes both external circuit data comprising a control command, and memory location data comprising a branch command, a jump address, and a status select command. Sequencer unit 24 selects a memory location in control store memory 20 to be currently accessed and therefore available to be transferred to pipeline register 22.
In response to a clock pulse from an external timing generator 52, the instruction in the control store memory location selected by sequencer unit 24 (including the control command, branch command, jump address and status select command) is transferred from control store memory 20 to pipeline register 22.
The instruction is then immediately transferred from pipeline register 22. Specifically, the control command of the instruction is immediately transferred to external operating circuit 50 over data link 38. The branch command and jump address are transferred to sequencer unit 24 over data links 32 and 34, respectively. The status select command is transferred to status select unit 26 over data link 36.
The control command specifies an operation or operations to be performed by external operating circuit 50 and directs operating circuit 50 to perform the specified operations. At the same time that pipeline register 22 transfers a control command to external Operating circuit 50, status select unit 26, which typically receives status signals 48 from external operating circuit 50, selects one of status signals 48 received from external operating circuit 50 in response to the status select command transferred to status select unit 26 from pipeline register 22. The selected status signal is then presented to sequencer unit 24 over data link 40.
Sequencer unit 24 receives the selected status signal from status select unit 26, and a branch command and jump address from pipeline register 22. Using the status signal, branch command and jump address received, sequencer unit 24 selects an address of a location in control store memory 20 which contains a next instruction containing operations to be performed by external operating circuit 50. Selection of the control store memory location containing the next instruction by sequencer unit 24 is operative to access the next instruction in control memory 20 and to make the instruction available for transfer to pipeline register 22 upon receipt by control store 20 of the next clock pulse from external timing generator 52.
FIG. 3 is a chart illustrating the operation of the prior art single pipeline sequencer of FIG. 1. As shown, at any given stage of operation the control store memory location currently accessed is that location, the address of which has been selected by sequencer unit 24. Pipeline register 22 contains information from the previous memory location accessed. Pipeline register 22 receives the instruction at the currently accessed location upon receipt by sequencer unit 24 of the clock pulse from external timing generator 52.
An example of a program segment with instructions for successive selection by conventional single pipeline sequencer 100 is set forth below (Table 1). The program segment shows memory addresses for the locations in control store memory 20, and the instruction lines contained at each location. Status select commands, where included as part of an instruction, branch commands, and jump addresses are shown.
TABLE 1 ______________________________________ Status Select Jump Address Address Command Branch Command True False ______________________________________ : : : 148 -- CONT 149 149 -- CONT 150 150 CNZ JMP 151 170 151 or : : 170 : : : : : ______________________________________
The first instruction of the exemplary program segment is located at control store memory location 148. Sequencer unit 24, when provided the CONT (meaning continue) branch command, selects the jump address in the "true" column and reads control store memory 20 to transfer the instruction at location 149 to pipeline register 22. A status select command is not specified for an instruction the branch command of which is a CONT. The instruction at location 149 is similar to the instruction at location 148. The next instruction transferred from control store memory 20 after the instruction at 149 is, therefore, the instruction at location 150.
The branch command for the instruction at location 150 is a JMP (meaning JUMP). Accordingly, sequencer unit 24 determines the location of the next instruction in accordance with a status signal from status select unit 26. The status select command is a CNZ (meaning CONDITION ZERO). If the "zero" condition is met, the status signal from status select unit 26 indicates a "true" condition. Alternatively, if the "zero" condition is not met, the status signal indicates a "false" condition. Sequencer unit 24 selects either jump address 151 or 170 depending on whether the status signal received from status select unit 26 indicates a "true" or "false" condition, respectively.
The selection of each address indicative of the next instruction to be transferred from control store memory 20 is based on the status select command, branch command and jump address appearing in the instruction last transferred from control store memory 20. It is possible to base the selection of the address for the next instruction on the memory location information, i.e., status select command, branch command and jump address contained in the last instruction transferred from control store memory since at the moment of transfer from control store memory 20 the memory location information (status select command, branch command, jump address) is immediately available at sequencer unit 24 through pipeline register 22. As a consequence, sequencer unit 24 has the information necessary to select the next successive instruction at the instant it becomes necessary to select a next location in control store memory 20 for access.
Although control commands are not shown in Table 1 for the control store memory locations, a control command exists for each location. The control commands are transferred to external operating circuit 50 when the status select command, branch command and jump address are transferred from control store memory 20. The control commands are executed by external operating circuit 0 of FIG. 1 while the address of the location of the next instruction is selected by sequencer unit 24.
The speed with which the single pipeline sequencer 100 operates is controlled by external timing generator 52. The length of time between clock pulses generated by external timing generator 52 is set in accordance with the system steps which must be performed between pulses. Between pulses, an instruction must be transferred to pipeline register 22 from control store memory 20, and from pipeline register 22 as described above (status select command to status select unit 26; branch command and jump address to sequencer unit 24; control command to external operating circuit 50). Also in the interval between pulses, a status signal must be selected by status select unit 26 and transferred to sequencer unit 24; sequencer unit 24 must select the address of the memory location containing the next instruction; and the next instruction must be accessed and made available for transfer from control store memory 20 to pipeline register 22. Because the steps, between and including the transfer of the instruction from control store memory 20 and the accessing of a next instruction for transfer from control store memory 20, must occur in the interval between pulses, a fixed limit exists as to how short the interval between pulses can be. That is, the operation speed for the sequencer system has a fixed time limit which cannot be exceeded.
The interval between pulses is shorter, i.e., the speed at which the system for providing external circuit data provides external operating circuit 50 with data is higher, for double pipeline sequencer 200 of FIG. 2.
Typically, double pipeline sequencer 200 includes apparatus and connections identical to the apparatus and connections for the single pipeline sequencer. In addition, however, the double pipeline sequencer includes pipeline register 28 as shown in FIG. 2. Sequencer unit 24 is connected to pipeline register 28 by a data link 44, and pipeline register 28 is coupled to control store memory 20 by data link 46. Data link 42, which exists between sequencer unit 24 and control store memory 20 for single pipeline sequencer 100, is eliminated.
Sequencer unit 24 of double pipeline sequencer 200 also selects an address of a location in control memory 20 having an instruction. As with single pipeline sequencer 100, the selection is in response to a status signal from status select unit 26 and a branch command and jump address from pipeline register 22. Sequencer unit 24 of double pipeline sequencer 200 is not, however, coupled to control store memory 20 and therefore does not operate to access the next instruction line in control store memory 20, and to make the next instruction line available for transfer from control store memory 20. After the address of the location containing the next instruction has been selected by sequencer unit 24, the address of the next instruction is retained in sequencer unit 24 until receipt of the next clock pulse from external timing generator 52.
In response to a clock pulse from external timing generator 52, the address retained in sequencer unit 24 is transferred to pipeline register 28. As described, pipeline register 28 is coupled to control store memory 20 by link 46. The receipt by control store memory 20 of the address of control store memory location containing the next instruction by pipeline register 28 is operative to access the instruction located at that address in control store memory 20 and make the instruction available for transfer from control store memory 20.
The next instruction stored in control store memory 20 is transferred to pipeline register 22 at a next successive clock pulse from timing generator 52. The instruction is then immediately transferred from pipeline register 22 in the same manner as described for conventional single pipeline sequencer 100. Sequencer unit 24 proceeds to select another next address of a control store memory location in which an instruction is stored.
The interval between clock pulses may be shorter for double pipeline sequencer 200 than for single pipeline sequencer 100 because of the inclusion of pipeline register 28. The interval between pulses may be reduced because sequencer unit 24 retains the address of the next instruction selected for transfer to pipeline register 28 at a next pulse. Time need not be allotted within the interval, therefore, for also transferring the selected next instruction address to control store memory 20, and for accessing the next instruction for transfer from control store memory 20. Because the clock pulse interval is shortened, the operating speed of the system is increased.
While pipeline register 28 causes a beneficial increase in the operating speed of the system, pipeline register 28 also detrimentally complicates the instruction lines which may be utilized by the conventional double pipeline sequencer.
Instruction lines are not immediately available for transfer from control store memory 20, after selection by sequencer unit 24. With double pipeline sequencer 200, the instruction at an address sequentially selected by sequencer unit 24 will be available to sequencer unit 24 for the selection of a next address only after the selected address has been transferred first to pipeline register 28 at a clock pulse, and then to pipeline register 22 from control store 20 at a successive clock pulse. It is only at the successive clock pulse which transfers the instruction from control store memory 20 to pipeline register 22 that the memory location data for that instruction becomes available to sequencer unit 24 for use in selecting a successive address of a control store memory location containing an instruction.
FIG. 4 is a chart illustrating the operation of the prior art double pipeline sequencer. As shown, at any given stage of operation, the control store memory location currently accessed is that location which was selected by sequencer unit 24 before the clock pulse transferring the address of that location to pipeline register 28. Pipeline register 22 receives the information from the memory location currently accessed at a next successive clock pulse from external timing generator 52.
Accordingly, the memory location data contained in any instruction cannot be used in the selection of the address for the next instruction. That is, sequencer unit 24 in response to a clock pulse will select a next address while the address last selected, in response to the same clock pulse, is transferred to pipeline sequencer 28. The last address selected, having not yet been transferred to pipeline register 22 at that clock pulse, is not operative to make the memory location information of the last instruction available to sequencer unit 24. The memory location data available to sequencer unit 24 at that clock pulse will be the memory location data contained in the instruction previous to the last instruction selected. Therefore, memory location data indicative of a next instruction to be selected by sequencer unit 24 must be contained in the instruction previous to the last instruction selected by sequencer unit 24 (a memory location data offset of two instructions).
An example of a program segment which could be utilized by a conventional double pipeline sequencer is set forth below (Table 2). The program segment shows addresses for locations in control store memory 20 and the instruction lines contained at each location. Status select commands, where included as part of an instruction, branch commands, and jump addresses are shown.
TABLE 2 ______________________________________ Status Select Jump Address Address Command Branch Command True False ______________________________________ : : : 148 -- CONT 150 149 CNZ JMP 151 170 150 -- CONT 152 151 or : : 170 : : : : : ______________________________________
The first instruction of the exemplary program segment is located at control store memory location 148. Sequencer unit 24, when provided the CONT branch command of the instruction at location 148, selects the jump address in the "true" column and retains memory location address 150 for later transfer to pipeline register 28. After a clock pulse, memory location 150 is transferred to pipeline register 28. After the same clock pulse, the instruction at location 149 becomes available to sequencer unit 24. The instruction line at location 149 contains a JMP branch command for causing a conditional jump (CNZ) after the instruction at location 150 has been executed.
It should be apparent from the example program segment and previous description that utilizing a double pipeline sequencer requires the use of memory location information in any given instruction which anticipates the instruction to be executed two instructions later. Anticipatory programming of this type is substantially more difficult than programming memory location information just one instruction ahead, as is required with conventional single pipeline sequencer 100.
Accordingly, an object of the present invention is to provide a system for sequentially providing external circuit data for an external circuit, which may be operated utilizing simple programming techniques, while yet operating at high speed.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description or may be learned by practice of the invention.